1. Field of the Invention
The present invention relates in general to semiconductor fabrication. More particularly, the invention relates to a process for fabricating a protective device for protecting semiconductor devices and circuits against electrostatic discharge (ESD).
2. Description of Related Art
Electrostatic discharge (ESD) protection can be provided for semiconductor devices using a dual diffusion source/drain (DDD) field effect transistor and a lightly doped source/drain (LDD) field effect transistor. The DDD field effect transistor provides better protection than the LDD field effect transistor. To enhance the ESD protection capability of the LDD field effect transistor, additional masking and ion implanting steps are required to raise the concentration of impurities in the LDD region.
FIGS. 1A-1C (Prior Art) are sectional diagrams of a semiconductor device depicting the steps of a conventional process for fabricating an ESD protective device. In each of these diagrams, the left half part shows the structure for the semiconductor device (hereinafter referred to as "functional region") intended to be protected by the conventional ESD protective device, and the right half part shows the structure for the conventional ESD protective device (hereinafter referred to as "ESD protective region").
Referring to FIG. 1A, in the first step a silicon substrate is 10 prepared and on which a gate electrode 12 is formed. Ions are implanted to form a lightly doped source/drain region 14.
Referring to FIG. 1B (Prior Art), subsequently an isolator 16 is formed on lateral sides of the gate electrode 12. Prior to forming the ESD protective device in the wafer, the isolator 16 must be removed by using a mask. In the subsequent step, another ion implantation is carried out with a high concentration of dopants, whereby the functional region is formed with an LDD structure and the ESD protective region is formed into a structure as shown in the right part of FIG. 1C (Prior Art). In this structure, the heavily doped region 18 in the source/drain electrode includes the originally formed lightly doped region 14, so that a better ESD protective effect is provided.
It is a drawback of the conventional process that, in order to provide the ESD protective region with high ESD capability and retain the LDD structure in the functional region, an additional mask must be used to remove the isolator 16 in the ESD protective region while retaining the isolator in the functional region. Moreover, in the step of forming metal silicide in the functional region by using self-aligning silicide process, another mask must be used to etch the metal silicide or to retard its growth.
Since the ESD is below 2000 V both for the LDD structure and the self-aligning silicide, the process is not suitable for use to form the ESD protective device. However, since the functional region must have such a structure, the use of two masks, one in the ESD protective region for etching the isolator and the other in the self-aligning silicide process for etching the metal silicide used for pattern definition, is quite costly for the overall fabrication process of the semiconductor device.